Computer architecture research uses simulation targets to quickly and cost-efficiently evaluate new ideas. Of these, Gem5 [1] is an open source simulator that supports multiple ISAs and provides a precise timing model of the full cache hierarchy and the memory subsystem [2]. Gem5 is even able to boot a full Linux system [3].

The goal of this thesis is to set up a testbed to evaluate memory interference effects on upcoming Arm platforms [4] and develop mitigations techniques (in hardware and/or software). On the software side, we use RT-Bench [5] and a research microkernel [6].

[1] www.gem5.org
[2] www.gem5.org/2020/06/01/heterogeneous-systems.html
[3] gem5art.readthedocs.io/en/latest/tutorials/boot-tutorial.html
[4] github.com/ARM-software/ATP-Engine/blob/master/README.md
[5] gitlab.com/rt-bench/rt-bench
[6] gitlab.com/azuepke/marron/

 

C, C++, Python, bash scripting

Basics of the computer architecture of modern SoCs and the Arm architecture in particular are helpful