Memory-Bandwidth Regulation for Arm and RISC-V Multicore SoC


In today's high performance multiprocessor system-on-a-chips, memory accesses are always the bottleneck.
Especially, the last-level cache, interconnects and memory controllers are shared between all cores in the system and therefore become a source of unpredictability for real-time applications.

To address this problem, researchers in real-time systems came up with novel approaches to apply per-core memory bandwidth regulation schemes, either in software (e.g. MemGuard [1] and MemPol [2]) or in hardware (e.g. BRU [3]).

The key approach of all these approaches is to:
1. monitor the per-core memory bandwidth use, e.g. by using performance counters
2. halt or throttle a core if the core exceeds its bandwidth budget
3. experiments with bandwidth regulation schemes

The idea of this thesis series is to implement, experiment and evaluate memory-bandwidth regulation techniques on current 64-bit multicore Arm and RISC-V SoCs that are used in industrial or automotive applications (e.g. NXP, TI, Nvidia, Microchip, Xilinx, ...).
For example, some of the SoCs have hardware performance counter units that can help to overcome the pessimism in memory bandwidth regulation (e.g. [4]).
The possibilities for memory bandwidth regulation approach depend on the actual SoC that should be explored in a semester thesis or master thesis.

As experimental test beds, we use Linux, but also the Jailhouse Hypervisor [5] and the Marron kernel [6].

[1] H. Yun et al.: MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. RTAS 2013. https://doi.org/10.1109/RTAS.2013.6531079

[2] A. Zuepke et al.: MemPol: Policing Core Memory Bandwidth from Outside of the Cores. RTAS 2023. https://doi.org/10.1109/RTAS58335.2023.00026

[3] F. Farshchi et al.: BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. RTAS 2020. https://doi.org/10.1109/RTAS48715.2020.00011

[4] A. Saeed et al.: Memory Utilization-Based Dynamic Bandwidth Regulation for Temporal Isolation in Multi-Cores. RTAS 2022. https://doi.org/10.1109/RTAS54340.2022.00019

[5] Jailhouse: https://github.com/siemens/jailhouse

[6] Marron Kernel: https://gitlab.com/azuepke/marron/

 

Requirements

C, Linux, Makefile, Bash, good understanding of computer architecture, embedded programming

Students from Informatics, Electrical Engineering or Mechanical Engineering can apply

 

Thesis Type

Semesterarbeit | Masterarbeit

Contact

Alex Züpke

Gebäude 5501 Raum 2.108

+49 (89) 289 - 55174

alex.zuepke@tum.de